The annealing algorithm
Constrained resource sharing and conflict resolution in Hebe
Integration, the VLSI Journal
Synthesis and simulation of digital systems containing interacting hardware and software components
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Multiple-process behavioral synthesis for mixed hardware-software systems
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Synthesis of system-level communication by an allocation-based approach
ISSS '95 Proceedings of the 8th international symposium on System synthesis
PARAS: system-level concurrent partitioning and scheduling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
The design of mixed hardware/software systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The heterogeneous structure problem in hardware/software codesign: a macroscopic approach
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Code placement in hardware/software co-synthesis to improve performance and reduce cost
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
A path-based technique for estimating hardware runtime in HW/SW-Cosynthesis
Readings in hardware/software co-design
Protocol selection and interface generation for HW-SW codesign
Readings in hardware/software co-design
Combining MBP-speculative computation and loop pipelining in high-level synthesis
EDTC '95 Proceedings of the 1995 European conference on Design and Test
The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Interface Optimization During Hardware-Software Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
An approach to the adaptation of estimated cost parameters in the COSYMA system
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
Previously, we had presented the system COSYMA for hardware/software co-synthesis of small embedded controllers. Target system of COSYMA is a core processor with application specific co-processors. The system speedup for standard programs compared to a single 33MHz RISC processor solution with fast, single cycle access RAM was typically less than 2 due to restrictions in high-level co-processor synthesis, and incorrectly estimated back end tool performance, such as hardware synthesis, compiler optimization and communication optimization. Meanwhile, a high-level synthesis tool for high-performance co-processors in co-synthesis has been developed. This paper explains the requirements and the main features of the high-level synthesis sytem and its integration into COSYMA. The results show a speedup of 10 in most cases. Compared to the speedup, the co-processor size is very small.