Architectural partitioning for system level design
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis and simulation of digital systems containing interacting hardware and software components
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis with pin constraints for multiple-chip designs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Partitioning by regularity extraction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Target architecture oriented high-level synthesis for multi-FPGA based emulation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (called PARAS) which can exploit this interaction by solving the scheduling and partitioning problems concurrently are presented. PARAS maximizes the overall performance of the final design and considers different chip configurations and communication structures. Experiments, conducted with specifications ranging in size from few to hundreds of operations, demonstrate the success of this approach.