Global hardware synthesis from behavioral dataflow descriptions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Redundant operator creation: a scheduling optimization technique
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Partitioning by regularity extraction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance-complexity analysis in hardware-software codesign for real-time systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
PARAS: system-level concurrent partitioning and scheduling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Architectural partitioning of control memory for application specific programmable processors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Synthesis of application specific programmable processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Procedure cloning: a transformation for improved system-level functional partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A methodology and algorithms for the design of hard real-time multitasking ASICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integrated test of interacting controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware-software cosynthesis for microcontrollers
Readings in hardware/software co-design
Readings in hardware/software co-design
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
High level synthesis: a data path partitioning method dedicated to speed enhancement
EURO-DAC '91 Proceedings of the conference on European design automation
Application of ESL synthesis on GSM edge algorithm for base station
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Architectural partitioning is introduced as a new phase in system level synthesis. Architectural partitioning extracts high level structure from the behavior of an architecture. This paper describes the APARTY architectural partitioner, an automatic Architectural PARTYtioner that supports synthesis in the System Architect's Workbench. APARTY uses a unique multi-stage clustering technique. Knowledge of the high level structure of an architecture aids synthesis tools in choosing a better design in terms of area. For one example, architectural partitioning reduced the number of wiring tracks in the final design by 20%.