Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques

Authors:
Miodrag Potkonjak;Wayne Wolf
Affiliations:
C&C Research Laboratories, NEC, Princeton, NJ;Dept. of EE, Princeton University, Princeton, NJ
Venue:
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Year:
1995

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Abstract

Abstract: Modern applications are often defined as sets of several computational tasks. This paper presents a synthesis algorithm for ASIC implementations which realize multiple computational tasks under hard real-time deadlines. The algorithm analyzes constraints imposed by task sharing as well as the traditional datapath synthesis criteria. In particular we demonstrated an efficient technique to combine rate-monotonic scheduling, a widely used hard real-time systems scheduling discipline, with estimations and scheduling and allocation algorithms. Matching the number of bits in tasks assigned to the same processor was the most important factor in obtaining good designs. We have demonstrated the effectiveness of our algorithms on several multiple-task examples.