The modeling and synthesis of bus systems
DAC '81 Proceedings of the 18th Design Automation Conference
Register-transfer level digital design automation: The allocation process
DAC '78 Proceedings of the 15th Design Automation Conference
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
Automated partitioning of hierarchically specified digital systems
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
The CMU design automation system: An example of automated data path design
DAC '79 Proceedings of the 16th Design Automation Conference
25 years of DAC Papers on Twenty-five years of electronic design automation
Partitioning by regularity extraction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Synthesis of application specific programmable processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The VLSI design automation assistant: what's in a knowledge base
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Synthesis by delayed binding of decisions
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Observations on comparing digital systems synthesis techniques
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
A methodology and algorithms for the design of hard real-time multitasking ASICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
High level synthesis: a data path partitioning method dedicated to speed enhancement
EURO-DAC '91 Proceedings of the conference on European design automation
Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages
The Journal of Supercomputing
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints
Integration, the VLSI Journal
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This paper describes an algorithm for partitioning a behavioral hardware description written in the ISPS computer hardware description language. The partitioning is done before the actual registers, processing elements, and interconnections have been chosen, so that the partitioning information can be used to guide the design of the data path structure. An experiment was conducted in which a partition produced by the algorithm was compared to partitions done by human designers. The automatic partition was found to be in close agreement with those done by the designers.