Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Architectural partitioning for system level design
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Real-Time Scheduling Theory and Ada
Computer
Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Architecture synthesis of high-performance application-specific processors
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Synthesis of application-specific multiprocessor architectures
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ATM scheduling with queuing delay predictions
SIGCOMM '93 Conference proceedings on Communications architectures, protocols and applications
Highly parallel computing (2nd ed.)
Highly parallel computing (2nd ed.)
Algorithm selection: a quantitative computation-intensive optimization approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A method for partitioning UNITY language in hardware and software
EURO-DAC '94 Proceedings of the conference on European design automation
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An efficient graph algorithm for FSM scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing lower bounds on functional units before scheduling
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Retargetable assembly code generation by bootstrapping
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
CodeSyn: a retargetable code synthesis system (abstract)
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
High level synthesis for reconfigurable datapath structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis of application specific programmable processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimal synthesis of multichip architectures
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Synthesis by delayed binding of decisions
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Analyzing the Multimedia Operating System
IEEE MultiMedia
Computer
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Scheduling for Reactive Real-Time Systems
IEEE Micro
Deadline-monotonic software scheduling for the co-synthesis of parallel hard real-time systems
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
The design of a low cost motion chair for video games and MPEG video playback
IEEE Transactions on Consumer Electronics
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software
IEEE Transactions on Software Engineering
A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems
Applied Soft Computing
Feedback fuzzy-DVS scheduling of control tasks
The Journal of Supercomputing
Optimization for real-time systems with non-convex power versus speed models
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Hi-index | 0.00 |
Traditional high-level synthesis concentrates on the implementation of a single task (e.g. filter, linear controller, A/D converter). However, many applications—multifunctional embedded controllers intelligent wireless end-points, and DSP and multimedia servers—are defined as sets of several computational tasks. This paper describes new techniques for the synthesis of ASIC implementations that realize multiple computational processes under hard real-time constraints. Our synthesis methodology establishes connections between two important comengineering domains: operating systems and behavioral synthesis. Our hierarchical approach starts from an incompletely-specified preliminary solution and uses, interchangeably, operating system and behavioral synthesis techniques to derive increasingly more detailed and accurate design solutions. We have experimented with both optimal and heuristic algorithms to implement this methodology. The optimal algorithm uses several heuristics to speed up the average run time of an exhaustive branch-and-bound search. Force-directed optimization is the core of the heuristic synthesis method. Analysis of the proposed algorithms and the experiments shows that matching the number of bits and type of operational in taskes assigned to the same application-specific processor was the most important factor in obtaining area-efficient designs.