A methodology and algorithms for the design of hard real-time multitasking ASICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiway FPGA partitioning by fully exploiting design hierarchy
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parameterised system design based on genetic algorithms
Proceedings of the ninth international symposium on Hardware/software codesign
Statistical design space exploration for application-specific unit synthesis
Proceedings of the 38th annual Design Automation Conference
Adaptive design using a genetic algorithm
Proceedings of the IFIP TC5/WG5.2 Workshop on Formal Design Methods for CAD
FPLD HDL synthesis employing high-level evolutionary algorithm optimisation
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
A parallel genetic algorithm for performance-driven VLSI routing
IEEE Transactions on Evolutionary Computation
An introduction to simulated evolutionary optimization
IEEE Transactions on Neural Networks
Predicting best design trade-offs: a case study in processor customization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we present a methodology for optimizing complex datapath oriented digital circuits. An optimizer was developed based on the earlier development of an automatic circuit synthesizer that synthesizes hardware description language specifications based on available functional modules. A genetic algorithm is tailored to the problem of digital circuit optimization through the development of specific structures and procedures. In particular, a concise encoding of the circuit is developed that the genetic algorithm can manipulate. Specific crossover and mutation mechanisms are also developed to complement the functionality of the synthesizer. The searches are effected by altering module data type, hardware resource sharing, and module implementation version. A fitness function is derived that makes use of a number of optimization parameters to objectively evaluate each particular circuit. The features of each circuit are calculated and estimated during the analysis phase.