System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
Timing models for high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Specification and design of embedded systems
Specification and design of embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A comprehensive estimation technique for high-level synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Reclocking for high-level synthesis
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Computing lower bounds on functional units before scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction set mapping for performance optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Sensitivity and Optimization
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Journal of Embedded Computing - Cache exploitation in embedded systems
A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems
Applied Soft Computing
IEEE Transactions on Circuits and Systems for Video Technology
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Proceedings of the Conference on Design, Automation and Test in Europe
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One of the primary advantages of a high-level synthesis system is its ability to explore the design space. This paper presents several methodologies for design space exploration that compute all optimal tradeoff points for the combined problem of scheduling, clock-length determination, and module selection. We discuss how each methodology takes advantage of the structure within the design space itself as well as the structure of, and interactions among, each of the three subproblems. (CAD)