Predicting area-time tradeoffs for pipelined design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
PLEST: a program for area estimation of VLSI integrated circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An object-oriented, procedural database for VLSI chip planning
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Automatic module allocation in high level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
A component selection algorithm for high-performance pipelines
EURO-DAC '94 Proceedings of the conference on European design automation
An exact methodology for scheduling in a 3D design space
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Clock optimization for high-performance pipelined design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Applications of attributed-behavior synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware resource allocation for hardware/software partitioning in the LYCOS system
Proceedings of the conference on Design, automation and test in Europe
Performance-constrained hierarchical pipelining for behaviors, loops, and operations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
1988 Design Automation Conference: Guest Editorial
IEEE Design & Test
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Towards a global solution to high level synthesis problems
EURO-DAC '90 Proceedings of the conference on European design automation
GRTL: a graphical platform for pipelined system design
EURO-DAC '91 Proceedings of the conference on European design automation
Optimum and heuristic synthesis of multiple word-length architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combining module selection and resource sharing for efficient FPGA pipeline synthesis
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Area-efficient arithmetic expression evaluation using deeply pipelined floating-point cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Module selection is one of the many functions which have to be performed during behavioral synthesis of pipelined designs. Module selection is the process of choosing the types of modules (e.g. carry-look-ahead adder) to implement each operation (e.g. addition). In this paper, we give a limited solution to the module selection problem for pipelined designs. A model for estimating area-time tradeoffs [3] for pipelined designs is used to formulate the module selection problem, and an overview of the solution technique is given. Complexities introduced by non-optimal designs and user constraints are also addressed. The results have been validated using designs generated by an automated pipeline synthesis program.