Scheduling high-level blocks for functional simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
LASSIE: structure to layout for behavioral synthesis tools
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A graphical hardware design language
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The use of Petri nets for modeling pipelined processors
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
A symbolic functional description language
DAC '84 Proceedings of the 21st Design Automation Conference
EURO-DAC '90 Proceedings of the conference on European design automation
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
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We present GRTL, a graphical design tool specifically for manual design of synchronous pipelines at the register transfer level. Abstractions (parameterized behavioral components, abstract signals) and AI methodology simplify input and reduce detail, yet useful timing analyses can be obtained. Features include integrated interactive design blackboard, Werner diagram and clocking formalisms for design correctness, open library, reversible functional simulator, and downloading facility for external silicon compilation. Earlier work is contrasted.