Interactive State-Space Analysis of Concurrent Systems
IEEE Transactions on Software Engineering
Petri nets and speed independent design
Communications of the ACM
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
A Generalized Timed Petri Net Model for Performance Analysis
International Workshop on Timed Petri Nets
Timed Petri nets and preliminary performance evaluation
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
ANALYSIS OF ASYNCHRONOUS CONCURRENT SYSTEMS BY TIMED PETRI NETS
ANALYSIS OF ASYNCHRONOUS CONCURRENT SYSTEMS BY TIMED PETRI NETS
Increasing user interaction during high-level synthesis
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
A top-down design environment for developing pipelined datapaths
DAC '98 Proceedings of the 35th annual Design Automation Conference
GRTL: a graphical platform for pipelined system design
EURO-DAC '91 Proceedings of the conference on European design automation
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
| Hi-index | 0.00 |
This paper discusses the use of Petri Nets for modeling and analyzing pipelined processors. Petri Nets are particularly well-suited to modeling the synchronization, buffering, resource contention and delicate timing so common in pipelined processors. Tools for simulating, animating and analyzing the behavior of the models are described. The usefulness of the tools and the analysis methods they support in evaluating the performance and analyzing the detailed timing of pipelined microprocessors is illustrated through an example.