System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
Timing models for high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Specification and design of embedded systems
Specification and design of embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Reclocking for high-level synthesis
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
A solution methodology for exact design space exploration in a three-dimensional design space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction set mapping for performance optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Sensitivity and Optimization
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware/software partitioning with integrated hardware design space exploration
Proceedings of the conference on Design, automation and test in Europe
Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
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One of the most compelling reasons for developing high-level synthesis systems has been the desire to quickly explore the design space. Since this problem is very difficult to solve optimally, most systems compute either lower bounds or estimates on the optimal tradeoff curve. The methodology described here goes beyond most previous work in several ways: (1) it computes all optimal tradeoff points so as to completely characterize the design space, (2) it solves not only the scheduling problem, but the clock determination and module selection problems as well, and (3) it carefully prunes the search space at each level of the design cycle.