An introduction to data structures with applications (2nd ed.)
An introduction to data structures with applications (2nd ed.)
An introduction to formal languages and automata
An introduction to formal languages and automata
Automatic operator configuration in the synthesis of pipelined architectures
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Computer system architecture (3rd ed.)
Computer system architecture (3rd ed.)
Generating pipelined datapaths using reduction techniques to shorten critical paths
EURO-DAC '92 Proceedings of the conference on European design automation
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The C++ standard library: a tutorial and reference
The C++ standard library: a tutorial and reference
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space
ISSS '96 Proceedings of the 9th international symposium on System synthesis
RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions
Proceedings of the 12th international symposium on System synthesis
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Much attention has been directed to different aspects of the design of pipelines [1,2,3,4]. Design of the control logic of non-linear pipelines has however, been considered as a subsidiary issue in that an RTL description for such logic can easily be obtained from a behavioral description, with the use of widely available synthesis tools. But, as the complexity of a non-linear pipeline increases, so does the complexity of the control logic. The complexity may be to an extent that obtaining even a behavioral description for the control logic is rendered difficult. This paper focuses on further automating the development of systems consisting of non-linear or multi-function pipelines by proposing an algorithmic technique for obtaining a behavioral description for the control logic of such pipelines. A simplified C++ implementation that produces a VHDL description of the control logic is then presented to clarify the algorithm.Experimental results that reveal connections between the nature of pipeline functions and the complexity of the control logic, obtained by utilization of the algorithm, are also presented. Consideration of these results can reduce the design space exploration of such pipelines to a more practically feasible subspace.