Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A First-Order Superscalar Processor Model
Proceedings of the 31st annual international symposium on Computer architecture
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficiently exploring architectural design spaces via predictive modeling
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Code transformation strategies for extensible embedded processors
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
A Predictive Performance Model for Superscalar Processors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
The impact of loop unrolling on controller delay in high level synthesis
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Spatial Sampling and Regression Strategies
IEEE Micro
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
Code transformation and instruction set extension
ACM Transactions on Embedded Computing Systems (TECS)
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design space exploration acceleration through operation clustering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Dominance-Based Multiobjective Simulated Annealing
IEEE Transactions on Evolutionary Computation
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Predicting best design trade-offs: a case study in processor customization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On learning-based methods for design-space exploration with high-level synthesis
Proceedings of the 50th Annual Design Automation Conference
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Hardware coprocessors are extensively used in modern heterogeneous systems-on-chip (SoC) designs to provide efficient implementation of application-specific functions. Customized coprocessor synthesis exploits design space exploration to derive Pareto optimal design configurations for a set of targeted metrics. Existing exploration strategies for coprocessor synthesis have been focused on either time consuming iterative scheduling approaches or ad-hoc sampling of the solution space guided by the designer's experience. In this paper, we introduce a meta-model assisted exploration framework that eliminates the aforementioned drawbacks by using response surface models (RSMs) for generating customized coprocessor architectures. The methodology is based on the construction of analytical delay and area models for predicting the quality of the design points without resorting to costly architectural synthesis procedures. Various RSM techniques are evaluated with respect to their accuracy and convergence. We show that the targeted solution space can be accurately modeled through RSMs, thus enabling a speedup of the overall exploration runtime without compromising the quality of results. Comparative experimental results, over a set of real-life benchmarks, prove the effectiveness of the proposed approach in terms of quality improvements of the design solutions and exploration runtime reductions. An MPEG-2 decoder case study describes how the proposed approach can be exploited for customizing the architecture of two hardware accelerated kernels.