Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A solution methodology for exact design space exploration in a three-dimensional design space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimizing compilers for modern architectures: a dependence-based approach
Optimizing compilers for modern architectures: a dependence-based approach
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Compiler optimization-space exploration
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Efficiently Searching the Optimal Design Space
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Interconnect Technology and Design for Gigascale Integration
Interconnect Technology and Design for Gigascale Integration
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Systematic dynamic memory management design methodology for reduced memory footprint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code transformation strategies for extensible embedded processors
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Design and Analysis of Experiments
Design and Analysis of Experiments
The impact of loop unrolling on controller delay in high level synthesis
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Cole: compiler optimization level exploration
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Optimal Unroll Factor for Reconfigurable Architectures
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
Code transformation and instruction set extension
ACM Transactions on Embedded Computing Systems (TECS)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bridging the gap between compilation and synthesis in the DEFACTO system
LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
Design space exploration acceleration through operation clustering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Performance optimization using template mapping for datapath-intensive high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using global code motions to improve the quality of results for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Design space exploration during high-level synthesis targets the computation of those design solutions which form optimal trade-off points. This quest for optimal trade-offs has been focused on studying the impact of various architectural-level parameters during high-level synthesis algorithms, silently neglecting the trade-offs produced from the combined impact of behavioral-level together with architectural-level parameters. We propose a novel design space, exploration methodology that studies an extended instance of the solution space considering the effects of combining compiler- and architectural-level transformations. It is shown that exploring the design space in a global manner reveals new trade-off points, thus shifting towards higher quality design solutions. We use a combination of upper-bounding conditions together with gradient-based heuristic pruning to efficiently traverse the extended search space. Our exploration framework delivers significant quality improvements without compromising the optimality (Pareto accuracy) of the discovered solutions, together with significant runtime reductions compared to exploring exhaustively the solution space at every allocation scenario.