Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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One of the primar,y trduuntages of a high-level synthesis system is its ability to explore the desiga space. This puper presents several methodologies for design space exploration that compute all optimal tradeoff points for the combined problem of scheduling, clock length determination, and module selection. We discuss how each methodology takes udvontuge of both the structure within the design space itself as well us the structure of, and interaction between, each of the three subproblems.