A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Performance-driven scheduling with bit-level chaining
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation
Regularity extraction via clan-based structural circuit decomposition
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Copy detection for intellectual property protection of VLSI designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Forward-looking objective functions: concept & applications in high level synthesis
Proceedings of the 39th annual Design Automation Conference
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A graph covering algorithm for a coarse grain reconfigurable system
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
CPR: A Configuration Profiling Tool
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient Logic Optimization Using Regularity Extraction
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The Journal of Supercomputing
Speedups in embedded systems with a high-performance coprocessor datapath
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pattern-based behavior synthesis for FPGA resource reduction
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
A Behavioral Synthesis Method with Special Functional Units
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Integration, the VLSI Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Frequent-pattern-guided multilevel decomposition of behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
HLS-l: high-level synthesis of high performance latch-based circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-path
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
High performance and area efficient flexible DSP datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Network flow based datapath bit slicing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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This paper introduces a new approach to performance-driven template mapping for high-level synthesis. Template mapping, the process of mapping high-level algorithmic descriptions to specialized hardware libraries or instruction sets, involves template matching, template selection, and clock selection. Efficient algorithms for each are presented, and novel issues such as partial matching are addressed. The paper focuses on datapath-intensive ASIC design, though the concepts are also highly applicable to compiler development. Experimental results on examples from real applications show significant improvements in throughput with limited area overhead