A signature based approach to regularity extraction
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Regularity extraction via clan-based structural circuit decomposition
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A regularity-driven fast gridless detailed router for high frequency datapath designs
Proceedings of the 2001 international symposium on Physical design
Regularity driven logic synthesis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Methodology for Synthesis of Data Path Circuitse
IEEE Design & Test
Efficient Logic Optimization Using Regularity Extraction
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Keep it straight: teaching placement how to better handle designs with datapaths
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Proceedings of the 49th Annual Design Automation Conference
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
Performance optimization using template mapping for datapath-intensive high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High performance and low power design techniques for ASIC and custom in nanometer technologies
Proceedings of the 2013 ACM international symposium on International symposium on physical design
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Proceedings of the International Conference on Computer-Aided Design
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In deep sub-micro designs, more functions are integrated into one chip, and datapath has become a critical part of the design. Typical datapath consists an array of bit slices. The inherent high degree regularity of datapaths is especially attractive to the placement and routing to achieve regular layout with high density and high performance. However, the current design methodology may generate inferior datapath designs because the datapath regularity cannot be well understood by the traditional design tools. In previous works, several techniques are proposed to preserve/re-identify datapath structures. However, they either restrict the datapath optimization or have little tolerance on bit slice difference. In this work, we present a novel approach to re-identify datapath bit slices. Contrary to the previous template-based approach, we convert the bit slicing problem to the bit matching problem. Then a min-cost max-flow based algorithm is proposed to identify the main-frame of bit slices so that the datapath bit matching is achieved. An efficient two way search approach is developed to derive the full bit slices based on the bit matching results. We further improve the bit slicing solution with an iterative method. The experimental results demonstrate the effectiveness and efficiency of our approach.