BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
A signature based approach to regularity extraction
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Regular layout generation of logically optimized datapaths
Proceedings of the 1997 international symposium on Physical design
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
DATAPATH: a CMOS data path silicon assembler
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Performance optimization using template mapping for datapath-intensive high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Network flow based datapath bit slicing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Proceedings of the International Conference on Computer-Aided Design
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This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural equivalence. The goal of the proposed algorithm is the speedup of logic optimization of large circuits by reusing functionally equivalent structures of the design. It is particularly suited for circuits containing a large amount of datapaths. The regularity extraction algorithm uses an AND/XOR representation of the netlist to allow high correlation of functional and structural equivalence. It then extracts regular structures, which can take any possible shape. The final optimization task is greatly reduced by optimizing only one copy of each regular structure while reusing the result for all other occurrences. In addition, structural regularity is widely preserved, resulting in higher packing density, shorter wiring length and improved delay during physical layout.