An efficient implementation of a scaling minimum-cost flow algorithm
Journal of Algorithms
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ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Introduction to algorithms
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Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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IEEE Design & Test
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ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Almost optimum placement legalization by minimum cost flow and dynamic programming
Proceedings of the 2004 international symposium on Physical design
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
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Proceedings of the 2006 international symposium on Physical design
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Proceedings of the 43rd annual Design Automation Conference
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
SafeChoice: a novel clustering algorithm for wirelength-driven placement
Proceedings of the 19th international symposium on Physical design
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IBM Journal of Research and Development
Keep it straight: teaching placement how to better handle designs with datapaths
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Proceedings of the 49th Annual Design Automation Conference
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
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Proceedings of the International Conference on Computer-Aided Design
Network flow based datapath bit slicing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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In this paper, we present a novel algorithm for latch placement, LatchPlanner which enables a placement engine to deliver high quality placement for datapath-oriented design. Datapath-oriented VLSI designs are in general hand-crafted by human at high cost, as understanding and capturing datapath structure is critical for the performance. The conventional placement algorithms by itself cannot exploit the underlying datapath due to lack of logic structure recognition and inaccurate/approximated wirelength estimation. LatchPlanner addresses such drawbacks by placing and fixing latches in the datapath context, a key element in datapath structure. By taking placed/fixed latches as constraints, a placer can find a more datapath-friendly placement effectively, which results in higher-quality hardware. LatchPlanner begins latch clustering/sizing/ordering to prepare the following steps, a) global latch placement based on linear programming to place latch clusters, and b) local latch placement based on network flow optimization to place latches within each cluster. Experimental results on eighteen industrial benchmarks show that LatchPlanner improves total wirelength by 32%, total negative slack by 25%, and area by 3% without CPU overhead over a commercial placement engine, and delivers near semi-custom-quality solutions.