Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Hard-Wired Multipliers with Encoded Partial Products
IEEE Transactions on Computers
A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
LILA: layout generation for iterative logic arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Data path placement with regularity
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Keep it straight: teaching placement how to better handle designs with datapaths
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Proceedings of the 49th Annual Design Automation Conference
Integrated placement and optimization flow for structured and regular logic
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Proceedings of the International Conference on Computer-Aided Design
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Proceedings of the International Conference on Computer-Aided Design
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Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test circuits. Algorithmic generation of netlists and of relative cell placement can help reducing area but, contrary to common belief, appears often detrimental to speed. Extraction of regularity from synthesized netlists is difficult and requires counterproductive simplifications to the synthesis process. Most promising are synthesis tools which can generate placement data; yet, no tool of this class appears ready today.