IEEE Spectrum - Special issue: technology 1997: analysis and forecast
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
Echelon: a multilayer detailed area router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LILA: layout generation for iterative logic arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Journal of VLSI Signal Processing Systems
An Integrated Approach to Semantic Evaluation and Content-Based Retrieval of Multimedia Documents
ECDL '98 Proceedings of the Second European Conference on Research and Advanced Technology for Digital Libraries
Design methodology for digital signal processing
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
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A new flexible datapath generator which allows the automated design of full-custom macros covering dedicated filter structures as well as programmable DSP cores is presented. The underlying concept combines the advantages of full-custom designs concerning power dissipation, silicon area, and throughput rate with a design effort comparable to semi-custom design styles. This is achieved by deriving all basic cells required for the macro layout from a set of so-called handcrafted leaf-cells by automatically generating the cell interconnections for each cell environment. Powerful routing routines based on a modified Lee-algorithm establish the interconnections within the cell boundaries, thereby avoiding unnecessary routing overhead. Since a small set of appropriately designed leaf-cells can cover a broad range of architectures the design effort is reduced significantly as compared to the pure full-custom style. Implementing new architectures typically requires the design of only a very small number of additional macro-specific leaf-cells for optimized core arrays. At the design entry the macro's functionality is described at word level as a so-called modified signal flow graph using VHDL. Optional parameters applied at this level provide a high degree of flexibility and support the careful optimization of the macro structure with short turnaround cycles. Moreover the datapath generator can be integrated into existing semi-custom design flows, enabling the embedding of optimized full-custom macros in overall semi-custom designs.