Module Generators for a Regular Analog Layout
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
A System for Designing Parallel Processor Arrays
EUROCAST '97 Proceedings of the A Selection of Papers from the 6th International Workshop on Computer Aided Systems Theory
ADPCM codec: from system level description to versatile HDL model
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
On core and more: a design perspective for systems-on-a-chip
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Unified Specification of Control and Data Flow
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
DSP Cores for Mobile Communications: Where Are We Going?
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Staying Ahead of the Game in Silicon for Digital Mobile Communications
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Reconfigurable Processing: The Solution to Low-Power Programmable DSP
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
VLSI Architecture for Datapath Integration of Arithmetic Over GF(2M) on Digital Signal Processors
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
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Improvements in semiconductor integration density and the resulting problem of having to manage designs of increasing complexity is an old one, but still current. The new challenge lies in a new level of architecture heterogeneity, e.g. mixing hard-wired digital circuits with software programmed signal processors on one die. Hence, we are moving by one level of abstraction from semi-custom standard-cells to semi-custom 'block cells'. This results in a new dimension in the gap between algorithm/system design and architecture/circuit design, not addressed by any tools sufficiently yet today. This paper presents a method of analyzing the problem by orthogonalizing algorithms into data transfer and data manipulation, and carrying this over to the control and I/O design as well. This approach might be a promising basis for flexibly mapping the algorithms onto future 'block cell' designs, and furthermore for designing new system simulation tools which allow for tools to be integrated for a flexible mapping of algorithms onto various different hardware architecture domains.