Adaptive filter theory
A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level VLSI Synthesis
Staying Ahead of the Game in Silicon for Digital Mobile Communications
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Advanced digital receiver principles and technologies for PCS
IEEE Communications Magazine
Design methodology for digital signal processing
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
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Due to the rapid increase in the system complexity of modern telecommunication products, two main challenges exist for a system design flow meeting the arising demands: 1) provide a platform for fast algorithmic and architectural design exploration and optimization from system to gate level, which guarantees high quality of results (QoR) and enables full and seamless design verification; 2) provide a platform for design reuse. In this paper, we show how a design flow based on fast system simulation, behavioral synthesis and power analysis is used for the commercial implementation of an ADPCM (Adaptive Differential Pulse Code Modulation) codec module in record time, simultaneously meeting all design constraints and creating a versatile system and HDL model ready for design reuse.