A data path layout assembler for high performance DSP circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Layout synthesis for datapath designs
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A timing-driven data path layout synthesis with integer programming
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '97 Proceedings of the 34th annual Design Automation Conference
A signature based approach to regularity extraction
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Regular layout generation of logically optimized datapaths
Proceedings of the 1997 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Relaxation and clustering in a local search framework: application to linear placement
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Analytical approach to custom datapath design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Regularity extraction via clan-based structural circuit decomposition
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
A regularity-driven fast gridless detailed router for high frequency datapath designs
Proceedings of the 2001 international symposium on Physical design
Design methodology for semi custom processor cores
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
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As more data processing functions are integrated into systems-on-chip, data path is becoming a critical part of the whole VLSI design. However, traditional physical design methodology can not satisfy the data path performance requirement because it has no knowledge of the data path bit-sliced structure. In this paper, an Abstract Physical Model (APM) is proposed to extract bit-slice regularity information from Data Flow Graph (DFG) and it is used for interconnect and congestion planning. A two step heuristic algorithm is introduced to optimize the linear placement of APM to satisfy both the wire length and routing track budget.