Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Transistor level placement for full custom datapath cell design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Automatic datapath tile placement and routing
Proceedings of the conference on Design, automation and test in Europe
Data path placement with regularity
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Transistor placement for noncomplementary digital VLSI cell synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design methodology for semi custom processor cores
Proceedings of the 14th ACM Great Lakes symposium on VLSI
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This paper addresses the problem of layout design automation of datapath cells. We present a novel approach to transistor placement problem for custom datapath designs and demonstrate that it can be applied to practical designs. Our approach is based on an analytical model which employs a mixed integer linear programming (MILP) technique. The novelty and originality of the method is the efficient management of the complexity of the underlying mathematical model. Our prototype tool automatically handles transistor merging, folding, and intra-cell component sharing.