BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Closing the gap between ASIC and custom: an ASIC perspective
Proceedings of the 37th Annual Design Automation Conference
The role of custom design in ASIC Chips
Proceedings of the 37th Annual Design Automation Conference
Analytical approach to custom datapath design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2002 international symposium on Low power electronics and design
Data path placement with regularity
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
In the Driver's Seat of BooleDozer
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
Low-power circuits and technology for wireless digital systems
IBM Journal of Research and Development
An innovative low-power high-performance programmable signal processor for digital communications
IBM Journal of Research and Development
Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors
IBM Journal of Research and Development
Custom circuit design as a driver of microprocessor performance
IBM Journal of Research and Development
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
Infrastructure requirements for a large-scale, multi-site VLSI development project
IBM Journal of Research and Development
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We describe a semi-custom design methodology for embedded processor cores that was prototyped through the development of a low power high performance DSP core. When compared to the standard ASIC design flow, this methodology enables significant improvement in the speed and power; such benefits are obtained without compromising the generality and flexibility that characterizes the ASIC-based design techniques. Our methodology achieves fast turn-around time in the process from RTL description to post-PD timing results, and exhibits stable convergence on timing; these characteristics enable the application of optimizations spanning multiple levels of the design hierarchy. Such optimizations proved to be much more effective than those that focus only on a single design stage.