Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
High speed CMOS design styles
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
CMOS system-on-a-chip voltage scaling beyond 50nm
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
A minimum total power methodology for projecting limits on CMOS GSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Clocking strategies and scannable latches for low power appliacations
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Introduction to 3G Mobile Communications
Introduction to 3G Mobile Communications
Low-Power CMOS Design
Low Power Digital CMOS Design
Low power integrated scan-retention mechanism
Proceedings of the 2002 international symposium on Low power electronics and design
Energy Considerations in Multichip-Module Based Multiprocessors
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Dynamic Flip-Flop with Improved Power
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Maintaining the benefits of CMOS scaling when scaling bogs down
IBM Journal of Research and Development
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Design methodology for semi custom processor cores
Proceedings of the 14th ACM Great Lakes symposium on VLSI
An innovative low-power high-performance programmable signal processor for digital communications
IBM Journal of Research and Development
Low-overhead state-retaining elements for low-leakage MTCMOS design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Proceedings of the 42nd annual Design Automation Conference
Enabling fine-grain leakage management by voltage anchor insertion
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
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As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the available system performance. This paper explores these questions and describes circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology.