MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
Low-power circuits and technology for wireless digital systems
IBM Journal of Research and Development
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Multi-threshold CMOS (MTCMOS) has shown to be a very effective technique for reducing sub-threshold leakage currents in DSM CMOS designs. Application of the MTC-MOS paradigm to sequential circuits requires the availability of data-retaining elements for storing circuit state during stand-by mode. In this paper we propose two novel circuit schemes for sequential elements featuring low leakage currents in stand-by mode and high-speed/low-dynamic power in active mode. We present post-layout simulation results obtained after parasitic extraction for delay and power of circuits built in 130nm CMOS technology. Our experiments demonstrate several advantages of the proposed schemes over the best previously published solutions.