MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
An MTCMOS design methodology and its application to mobile computing
Proceedings of the 2003 international symposium on Low power electronics and design
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
Low-power circuits and technology for wireless digital systems
IBM Journal of Research and Development
Optimal sleep transistor synthesis under timing and area constraints
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Functional unit shutdown based on MTCMOS devices is effective for leakage reduction in aggressively scaled technologies. However, the applicability of MTCMOS-based shutdown in a synthesis-based design flow poses the challenge of interfacing logic blocks in shutdown mode with active units: The outputs of inactive gates can float at intermediate voltages, causing very large short-circuit currents in the active gates they drive.In this paper, we propose two novel low-overhead elementary cells that fully address this issue. These cells can be added to any synthesis library, and they can be inserted into a netlist at the boundary between shutdown and active regions. Our results show that: (i) Our cells solve the interfacing problem with minimum overhead; (ii) A non-intrusive design flow enhancement is sufficient to automatically insert interface cells in post-synthesis netlists.