MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Analysis and optimization of gate leakage current of power gating circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Enabling fine-grain leakage management by voltage anchor insertion
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Physical design methodology of power gating circuits for standard-cell-based design
Proceedings of the 43rd annual Design Automation Conference
Sleep transistor distribution in row-based MTCMOS designs
Proceedings of the 17th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal sleep transistor synthesis under timing and area constraints
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Power-gating-aware high-level synthesis
Proceedings of the 13th international symposium on Low power electronics and design
Proceedings of the conference on Design, automation and test in Europe
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A robust power gating structure and power mode transition strategy for MTCMOS design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Supply switching with ground collapse for low-leakage register files in 65-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis and implementation of active mode power gating circuits
Proceedings of the 47th Design Automation Conference
Design and optimization of power-gated circuits with autonomous data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are used to implement the desired function, the high Vth transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsung's 0.18?m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18?m process. The fabricated PDA processor operates at 333MHz, and consumes about 2?W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.