Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Automated selective multi-threshold design for ultra-low standby applications
Proceedings of the 2002 international symposium on Low power electronics and design
An MTCMOS design methodology and its application to mobile computing
Proceedings of the 2003 international symposium on Low power electronics and design
Reverse-body bias and supply collapse for low effective standby power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Physical design methodology of power gating circuits for standard-cell-based design
Proceedings of the 43rd annual Design Automation Conference
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses
IEEE Design & Test
Power-gating-aware high-level synthesis
Proceedings of the 13th international symposium on Low power electronics and design
Supply switching with ground collapse for low-leakage register files in 65-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design and optimization of power-gated circuits with autonomous data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Power gating has been widely used to reduce subthreshold leakage. However, the efficiency of power gating degrades very fast with technology scaling, which we demonstrate by experiment. This is due to the gate leakage of circuits specific to power gating, such as storage elements and output interface circuits with a data-retention capability. A new scheme called supply switching with ground collapse is proposed to control both gate and subthreshold leakage in nanometer-scale CMOS circuits. Compared to power gating, the leakage is cut by a factor of 6.3 with 65-nm and 8.6 with 45-nm technology. Various issues in implementing the proposed scheme using standard-cell elements are addressed, from register transfer level to layout. These include the choice of standby supply voltage with circuits that support it, a power network architecture for designs based on standard-cell elements, a current switch design methodology, several circuit elements specific to the proposed scheme, and the design flow that encompasses all the components. The proposed design flow is demonstrated on a commercial design with 90-nm technology, and the leakage saving by a factor of 32 is observed with 3% and 6% of increase in area and wirelength, respectively.