Digital systems engineering
SRT Division Architectures and Implementations
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Future performance challenges in nanometer design
Proceedings of the 38th annual Design Automation Conference
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Constructive benchmarking for placement
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Design methodology for semi custom processor cores
Proceedings of the 14th ACM Great Lakes symposium on VLSI
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design, layout and verification of an FPGA using automated tools
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Explaining the gap between ASIC and custom power: a custom perspective
Proceedings of the 42nd annual Design Automation Conference
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Full-custom vs. standard-cell design flow: an adder case study
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A methodology for FPGA to structured-ASIC synthesis and verification
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Physical realization oriented area-power-delay tradeoff exploration
SOC'09 Proceedings of the 11th international conference on System-on-chip
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
Full-custom VLSI design of a unified multiplier for elliptic curve cryptography on RFID tags
Inscrypt'09 Proceedings of the 5th international conference on Information security and cryptology
21st century digital design tools
Proceedings of the 50th Annual Design Automation Conference
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Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Through floorplanning and tiling data paths, the designer places the critical wires first, before the logic is placed. Crafted datapath cells structure wiring at the other end of the spectrum by keeping local wires short enabling the use of minimum sized drivers. Routing the wires first gives early visibility of timing issues, allows the design to be optimized to drive the exact wire load, and enables the use of fast circuit styles.