Closing the gap between ASIC and custom: an ASIC perspective
Proceedings of the 37th Annual Design Automation Conference
The role of custom design in ASIC Chips
Proceedings of the 37th Annual Design Automation Conference
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
High speed, low power 8t full adder cell with 45% improvement in threshold loss problem
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
A novel CMOS 1-bit 8T full adder cell
WSEAS TRANSACTIONS on SYSTEMS
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Full-custom design is considered superior to standard-cell design when a high-performance circuit is requested. The structured routing of critical wires is considered to be the most important contributor to this performance gap. However, this is only true for bitsliced designs, such as ripple-carry adders, but not for designs with inter-bitslice interconnections spanning several bitslices, such as tree adders and reduction-tree multipliers. It is found that standard-cell design techniques scale better with the data width than full-custom bitsliced layouts for designs dominated by inter-bitslice interconnections.