Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A Novel Low Power Energy Recovery Full Adder Cell
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Full-custom vs. standard-cell design flow: an adder case study
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
9T full adder design in subthreshold region
VLSI Design
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The 1-bit full adder is a very important component in the design of application specific integrated circuits. Demands for the low power VLSI have been pushing the development of design methodologies aggressively to reduce the power consumption drastically. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is the main design aspect. The present study proposes a novel CMOS 1-bit full adder cell with least MOS transistor count that reduces the serious problem of threshold loss. It considerably increases the speed and also proves best for high frequency applications. Result shows 45% improvement in threshold loss problem and considerable reduction in power consumption over the other types of adders with comparable performance. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm and 130nm technologies.