9T full adder design in subthreshold region

Authors:
Shiwani Singh;Tripti Sharma;K. G. Sharma;B. P. Singh
Affiliations:
Faculty of Engineering & Technology, MITS, Deemed University, India;Department of Electronics & Communication, Suresh Gyan Vihar University, Jaipur, India;Department of Electronics & Communication, Suresh Gyan Vihar University, Jaipur, India;Faculty of Engineering & Technology, MITS, Deemed University, India
Venue:
VLSI Design
Year:
2012

Citing 3
Cited 0

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A novel CMOS 1-bit 8T full adder cell

WSEAS TRANSACTIONS on SYSTEMS

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Abstract

This paper presents prelayout simulations of two existing 9T and new proposed 9T full adder circuit in subthreshold region to employ in ultralow-power applications. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power-delay product (PDP) and improves temperature sustainability when compared with existing 9T adders. Therefore, in a nut shell proposed adder cell outperforms the existing adders in subthreshold region and proves to be a viable option for ultralow-power and energy-efficient applications. All simulations are performed on 45nm standard model on Tanner EDA tool version 13.0.