Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
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This paper illustrates a method to determine the optimal voltage, wire sizing and repeater insertion design rules for a global wire routing level that uses wave-pipelined interconnect circuits. In order to balance performance, power and area, a throughput-per-energy-area (TPEA) metric is introduced to guide the design of a global wire routing level to achieve maximum throughput (i.e. bit-rate) with optimal utilization of resources. A 180nm technology case study for a memory bus channel that requires an aggregate throughput of 332.8Gbps illustrates that the optimal TPEA combination of 1V supply, 6 repeaters per centimeter, a metal thickness to width aspect ratio of 2.5 and metal pitch to width ratio of 3 gives 12% reduction in dynamic power and over 60% reduction in wire area as compared to a published interconnect circuit that uses low voltage differential signaling (LVDS).