Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Modern vlsi design: system-on-chip design, third edition
Modern vlsi design: system-on-chip design, third edition
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In future many-core microprocessors, on-chip global interconnect links between cores have significant effects on the overall system performance. Improving the throughput and reducing the huge power dissipation in such global links is essential for enabling such future many-core microprocessors. In deep-submicron technologies, intrinsic gate delays are significantly reduced, resulting in very small signal transition times and injecting high frequency components into the interconnects. Hence, inductance and transmission line effects cannot be ignored. In this paper, the design of a global interconnect link for data communication in many-core microprocessors is presented. The presented design is based on having the interconnect designed and excited as a transmission line with low losses to enable near speed-of-light on-chip propagation on global wires with high data bandwidth and low power dissipation. Replacing the conventional repeater insertion in long global interconnects with the presented design results in significant improvements in all aspects of performance.