Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
The role of custom design in ASIC Chips
Proceedings of the 37th Annual Design Automation Conference
Clock rate versus IPC: the end of the road for conventional microarchitectures
Proceedings of the 27th annual international symposium on Computer architecture
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Microarchitecture evaluation with physical planning
Proceedings of the 40th annual Design Automation Conference
A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-µm CMOS Viterbi Decoder
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
DSPxPlore: design space exploration methodology for an embedded DSP core
Proceedings of the 2004 ACM symposium on Applied computing
Reuse Methodology Manual for System-on-a-Chip Designs
Reuse Methodology Manual for System-on-a-Chip Designs
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
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High level design-space exploration methodologies focus on optimizations on application and architectural abstraction layer. For power, leakage, and cost sensitive, as well as for performance critical SoC building blocks like embedded domain-specific processors and application specific accelerators, parasitic physical realization effects strongly influence the actual architecture efficiency. The tradeoff between architectural choices and physical implementation consequences needs to be considered to optimize area-power-performance efficiency. In this paper a semi-automated methodology is described that supports architectural optimizations with quantitative feedback on physical realizations already in an early design-space exploration phase. The presented methodology accounts for parasitic effects at the physical realization level, enables an efficient quantitative implementation tradeoff exploration for the design of high-performance SoC building blocks, and provides the foundation for a directed optimization throughout the design process.