Low-latency architectures for high-throughput rate viterbi decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-latency low-complexity architectures for Viterbi decoders
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Physical realization oriented area-power-delay tradeoff exploration
SOC'09 Proceedings of the 11th international conference on System-on-chip
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
Design space exploration of hard-decision Viterbi decoding: algorithm and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hardware-efficient technique to implement a trellis code modulation decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a 20-Mb/s 256-state viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In today's high-speed disk drive read channel ICs maximum likelihood detection using the Viterbi algorithm is a key component in reconstructing digital data sequences. The presented Viterbi decoder was realized in a 0.25-µm CMOS technology. Using the proposed comparison approach, it achieves a throughput rate of 550 Mb/s.