A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-µm CMOS Viterbi Decoder
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Low-latency architectures for high-throughput rate viterbi decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Look-ahead techniques are applied in the nonlinear add-compare-select unit for achieving high throughput in Viterbi decoders. Multiple steps of the binary trellis are combined into an equivalent one-step complex trellis in time sequence, which is referred to as the branch metric precomputation (BMP). As the look-ahead level increases, the BMP dominates the complexity and delay of the overall system architecture. This paper systematically proposes an optimal branch metric computation scheme with the minimal complexity and latency. The proof of its optimality is also given. This highly efficient scheme leads to a novel overall optimal BMP architecture for any look-ahead level. Furthermore, an alternative technique other than the look-ahead is proposed for reducing the latency at very low complexity cost. This alternative technique can be either applied in combination with the proposed architecture to achieve the lowest latency at a slight increase in complexity or used on its own for low complexity compared with other look-ahead-based architectures. Results show that the three proposed architectures can either reduce complexity by up to 84% or reduce the latency by up to 72.50%.