A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-µm CMOS Viterbi Decoder
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Low-latency low-complexity architectures for Viterbi decoders
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Design space exploration of hard-decision Viterbi decoding: algorithm and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high-throughput rate Viterbi decoders. The proposed method guarantees parallel paths between any two-trellis states in the look-ahead trellises and distributes the add-compare-select (ACS) computations to all trellis layers. It leads to regular and simple architecture for the Viterbi decoding algorithm. The look-ahead ACS computation latency of the proposed method increases logarithmically with respect to the look-ahead step (M) divided by the encoder constraint length (K) as opposed to linearly as in prior work. For a 4-state (i.e., K = 3) convolutional code, the decoding latency of the Viterbi decoder using proposed method is reduced by 84%, at the expense of about 22% increase in hard-ware complexity, compared with conventional M-step look-ahead method with M = 48 (where M is also the level of parallelism). The main advantage of our proposed design is that it has the least latency among all known look-ahead Viterbi decoders for a given level of parallelism.