A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis
VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis
A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-µm CMOS Viterbi Decoder
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Low-latency architectures for high-throughput rate viterbi decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trace back techniques adapted to the surviving memory management in the M algorithm
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 06
IEEE Transactions on Signal Processing
IC design of an adaptive Viterbi decoder
IEEE Transactions on Consumer Electronics
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Viterbi algorithm is widely used as a decoding technique for convolutional codes as well as a bit detection method in storage devices. The design space for VLSI implementation of Viterbi decoders is huge, involving choices of throughput, latency, area, and power. Even for a fixed set of parameters like constraint length, encoder polynomials and trace-back depth, the task of designing a Viterbi decoder is quite complex and requires significant effort. Sometimes, due to incomplete design space exploration or incorrect analysis, a suboptimal design is chosen. This work analyzes the design complexity by applying most of the known VLSI implementation techniques for hard-decision Viterbi decoding to a different set of code parameters. The conclusions are based on real designs for which actual synthesis and layouts were obtained. In authors' view, due to the depth covered, it is the most comprehensive analysis of the topic published so far.