A fast ACSU architecture for Viterbi decoder using T-algorithm
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Design space exploration of hard-decision Viterbi decoding: algorithm and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel high-throughput limited search trellis decoder VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a 20-Mb/s 256-state viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We implement an integrated circuit (IC) design for a decoder of a 64-state binary convolutional code. The decoder is based on a reduced-state adaptive Viterbi algorithm (VA) for which the decoding speed is faster than the standard VA while the error performance remains almost the same. With the adaptive VA, less bits are needed to store and to calculate the metrics of the decoding trellis and less power dissipation is needed, as compared to the standard VA. The IC design is based on a 0.8 μm CMOS technology. The number of quantization levels in the decoding is Q=8