Proceedings of the 2006 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design space exploration of hard-decision Viterbi decoding: algorithm and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel high-throughput limited search trellis decoder VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder
Journal of Signal Processing Systems
| Hi-index | 35.68 |
Significant power reduction can be achieved by exploiting real-time variation in system characteristics. An approach is proposed and studied herein that exploits variation in signal transmission system characteristics to reduce power consumption while decoding convolutional codes. With this approach, Viterbi decoding is adaptively approximated by varying the pruning threshold of the T-algorithm and truncation length while employing trace-back memory management. A heuristic is given for finding and adaptively applying pairs of pruning threshold and truncation length values that significantly reduce power to variations in signal-to-noise ratio (SNR), code rate, and maximum acceptable bit-error rate (BER). The power reduction potential of different levels of adaptation is studied. High-level energy reduction estimates of 80% to 97% compared with Viterbi decoding are shown. Implementation insight and general conclusions about when applications can particularly benefit from this approach are given.