A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications

Authors:
Jie Jin;Chi-Ying Tsui
Affiliations:
Hong Kong University of Science and Technology, Kowloon, Hong Kong;Hong Kong University of Science and Technology, Kowloon, Hong Kong
Venue:
Proceedings of the 2006 international symposium on Low power electronics and design
Year:
2006

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Abstract

This paper presents a low power Viterbi decoder design based on Scarce State Transition (SST). We propose an approach which seamlessly integrates the path pruning techniques with the SST decoding to reduce the average add-compare-select (ACS) computation. The scheme has very low overhead and is practical for implementation. We also propose an uneven-partitioned memory architecture for the survivor memory unit to reduce the memory access power during the trace back operation. The proposed decoder is implemented in SMIC 0.18?m CMOS process. Simulation results show that significant power consumption reduction can be achieved for high throughput wireless systems such as MB-OFDM Ultra-wide-band applications.