JouleTrack: a web based tool for software energy profiling
Proceedings of the 38th annual Design Automation Conference
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A dynamically reconfigurable adaptive viterbi decoder
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations
Proceedings of the 2002 international symposium on Low power electronics and design
Adaptation techniques in wireless packet data services
IEEE Communications Magazine
Proceedings of the 2006 international symposium on Low power electronics and design
Incremental elaboration for run-time reconfigurable hardware designs
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric Design for Reconfigurable Software-Defined Radio
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
High speed biological sequence analysis with hiddenMarkov models on reconfigurable platforms
IEEE Transactions on Information Technology in Biomedicine - Special section on computational intelligence in medical systems
Design and measurement of a variable-rate Viterbi decoder in 130-nm digital CMOS
Microprocessors & Microsystems
Power characterisation for fine-grain reconfigurable fabrics
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
A low-complexity viterbi decoder for space-time trellis codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
ISBA: an independent set-based algorithm for automated partial reconfiguration module generation
Proceedings of the International Conference on Computer-Aided Design
Dynamic partial reconfigurable Viterbi decoder for wireless standards
Computers and Electrical Engineering
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Error-correcting convolutional codes provide a proven mechanism to limit the effects of noise in digital data transmission. Although hardware implementations of decoding algorithms, such as the Viterbi algorithm, have shown good noise tolerance for error-correcting codes, these implementations require an exponential increase in very large scale integration area and power consumption to achieve increased decoding accuracy. To achieve reduced decoder power consumption, we have examined and implemented decoders based on the reduced-complexity adaptive Viterbi algorithm (AVA). Run-time dynamic reconfiguration is performed in response to varying communication channel-noise conditions to match minimized power consumption to required error-correction capabilities. Experimental calculations indicate that the use of dynamic reconfiguration leads to a 69% reduction in decoder power consumption over a nonreconfigurable field-programmable gate array implementation with no loss of decode accuracy.