Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Proceedings of the 42nd annual Design Automation Conference
A reconfigurable, power-efficient adaptive Viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal reconfiguration sequence management
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices
IEEE Transactions on Computers
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Floorplan Design for Multimillion Gate FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning for Partially Reconfigurable FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Approximating the maximum weight clique using replicator dynamics
IEEE Transactions on Neural Networks
Dynamic configuration prefetching based on piecewise linear prediction
Proceedings of the Conference on Design, Automation and Test in Europe
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Dynamic Partial Reconfiguration (DPR) on FPGAs has attracted significant research interests in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in current DPR design flow, leveraging these benefits requires specific designer expertise with laborious manual design effort. Considering the complicated concurrency relations among functions, it is challenging to properly select Partial Reconfiguration Modules (PR Modules) and partition them into groups so that the hardware modules can be swapped in and out during the run time. What's more, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we formulate the PR Module generation problem into a standard Maximum-Weight Independent Set Problem (MWISP) so that the original manual exploration can be solved optimally and automatically. Our proposed algorithm not only supports various design constraints, but also has the ability to consider multiple objectives such as area and reconfiguration delay. Experimental results show that our approach can optimize resource utilization and reduce reconfiguration delay with good scalability. Especially, the implementation of the real design case shows that our approach can be embedded in the Xilinx's DPR design flow successfully and it can save around 70% reconfiguration latency overhead compared with the heuristic PR Module generation approaches.