FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Proceedings of the 30th annual international symposium on Computer architecture
Instruction Scheduling for Dynamic Hardware Configurations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Proceedings of the 42nd annual Design Automation Conference
Piecewise Linear Branch Prediction
Proceedings of the 32nd annual international symposium on Computer Architecture
Transmuting coprocessors: dynamic loading of FPGA coprocessors
Proceedings of the 46th Annual Design Automation Conference
Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications
Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications
From Instruction Traces to Specialized Reconfigurable Arrays
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
Design Optimizations for Tiled Partially Reconfigurable Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISBA: an independent set-based algorithm for automated partial reconfiguration module generation
Proceedings of the International Conference on Computer-Aided Design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Energy-aware design of secure multi-mode real-time embedded systems with FPGA co-processors
Proceedings of the 21st International conference on Real-Time Networks and Systems
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Modern systems demand high performance, as well as high degrees of flexibility and adaptability. Many current applications exhibit a dynamic and nonstationary behavior, having certain characteristics in one phase of their execution, that will change as the applications enter new phases, in a manner unpredictable at design-time. In order to meet the performance requirements of such systems, it is important to have on-line optimization algorithms, coupled with adaptive hardware platforms, that together can adjust to the run-time conditions. We propose an optimization technique that minimizes the expected execution time of an application by dynamically scheduling hardware prefetches. We use a piecewise linear predictor in order to capture correlations and predict the hardware modules to be reached. Experiments show that the proposed algorithm outperforms the previous state-of-art in reducing the expected execution time by up to 27% on average.