The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
Journal of Signal Processing Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Novo-G: At the Forefront of Scalable Reconfigurable Supercomputing
Computing in Science and Engineering
Fast multidimension multichoice knapsack heuristic for MP-SoC runtime management
ACM Transactions on Embedded Computing Systems (TECS)
Performance of multi-threaded execution in a shared-memory multiprocessor
SPDP '91 Proceedings of the 1991 Third IEEE Symposium on Parallel and Distributed Processing
IEEE Transactions on Consumer Electronics
Dynamic configuration prefetching based on piecewise linear prediction
Proceedings of the Conference on Design, Automation and Test in Europe
Microprocessors & Microsystems
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Resource run-time managers have been shown particularly effective for coordinating the usage of the hardware resources by multiple applications, eliminating the necessity of a full-blown operating system. For this reason, we expect that this technology will be increasingly adopted in emerging multi-application reconfigurable systems. This paper introduces a fully automated design flow that exploits multi-objective design space exploration to enable run-time resource management for the Molen reconfigurable architecture. The entry point of the design flow is the application source code; our flow is able to heuristically determine a set of candidate hardware/software configurations of the application (i.e., operating points) that trade off the occupation of the reconfigurable fabric (in this case, an FPGA), the load of the master processor and the performance of the application itself. This information enables a run-time manager to exploit more efficiently the available system resources in the context of multiple applications. We present the results of an experimental campaign where we applied the proposed design flow to two reference audio applications mapped on the Molen architecture. The analysis proved that the overhead of the design space exploration and operating points extraction with respect to the original Molen flow is within reasonable bounds since the final synthesis time still represents the major contribution. Besides, we have found that there is a high variance in terms of execution time speedup associated with the operating points of the application (characterized by a different usage of the FPGA) which can be exploited by the run-time manager to increase/decrease the quality of service of the application depending on the available resourcess.